A clock and data recovery (CDR) circuit extracting a clock from received data and restoring the received data has been used in a receiving circuit. The CDR circuit is largely divided into two types, i.e., a type using a reference clock and a type that does not use a reference clock (reference clockless CDR circuit). The type using a reference clock generates a frequency according to a data rate by using a phase locked loop (PLL) circuit. For this reason, the CDR circuit of the type that uses a reference clock does not have a frequency adjusting function. The reference clockless (the type that does not use a reference clock) CDR circuit generates a clock signal of a frequency according to a data rate by using the CDR circuit. For this reason, the CDR circuit of the type that does not use a reference clock has a frequency adjusting function.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2013-135423 and Japanese Laid-Open Patent Publication No. 11-331135.